A case study of integer sum reduction using atomics

Zheming Jin, Hal Finkel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents the implementations of integer sum reduction using atomic functions on FPGA, CPU, and GPU platforms. We explain the implementations and optimizations of the kernel using an OpenCL-based high-level synthesis flow for an FPGA. In addition, we describe the optimizations of the reduction using directives for a multi-core CPU and a GPU. The experimental results show that the reduction on an Nvidia K80 GPU is 3.4X and 6.7X faster than an Intel Xeon 16-core CPU and an Arria 10 GX1150 FPGA, respectively. However, the FPGA consumes 4.4X and 2.3X less power than the CPU and GPU, respectively. The performance per watt on the FPGA is 2.2X higher than that on the CPU and 2.9X lower than that on the GPU.

Original languageEnglish
Title of host publicationProceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450365420
DOIs
StatePublished - Jun 20 2018
Externally publishedYes
Event9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018 - Toronto, Canada
Duration: Jun 20 2018Jun 22 2018

Publication series

NameACM International Conference Proceeding Series

Conference

Conference9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018
Country/TerritoryCanada
CityToronto
Period06/20/1806/22/18

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