TY - JOUR
T1 - A 6F2 DRAM technology in 60nm era for gigabit densities
AU - Cho, Changhyun
AU - Song, Sangho
AU - Kim, Sangho
AU - Jang, Sungho
AU - Lee, Sungsam
AU - Kim, Hyungtak
AU - Sung, Yangsoo
AU - Jeon, Sangmin
AU - Yeo, Gisung
AU - Kim, Youngsun
AU - Kim, Yungi
AU - Jin, Gyoyoung
AU - Kim, Kinam
PY - 2005
Y1 - 2005
N2 - A novel process technology for 6F2 DRAM cell at 68nm design rule was for the first time developed. The cell size is 0.028μm2, which is the smallest cell size ever reported. ArF lithography with double expose technology and highly selective etching process were used for patterning of critical layers. This 6F2 cell was made of simple line/space patterns for easy patterning and self-aligned etches to improve process margins. MIM cell capacitor was developed with multi-layer high-k dielectric materials and 11Å equivalent Tox and sub-1fA leakage was confirmed.
AB - A novel process technology for 6F2 DRAM cell at 68nm design rule was for the first time developed. The cell size is 0.028μm2, which is the smallest cell size ever reported. ArF lithography with double expose technology and highly selective etching process were used for patterning of critical layers. This 6F2 cell was made of simple line/space patterns for easy patterning and self-aligned etches to improve process margins. MIM cell capacitor was developed with multi-layer high-k dielectric materials and 11Å equivalent Tox and sub-1fA leakage was confirmed.
UR - http://www.scopus.com/inward/record.url?scp=33745140874&partnerID=8YFLogxK
U2 - 10.1109/.2005.1469202
DO - 10.1109/.2005.1469202
M3 - Conference article
AN - SCOPUS:33745140874
SN - 0743-1562
VL - 2005
SP - 36
EP - 37
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
M1 - 1469202
T2 - 2005 Symposium on VLSI Technology
Y2 - 14 June 2005 through 14 June 2005
ER -