Abstract
This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20 $\Omega $ is used as a transmitter (TX) impedance instead of 50 $\Omega $. To maximize eye openings further, fractionally spaced feedforward equalization (FS-FFE) is used with a tap spacing of 0.8 UI. The relaxed termination scheme along with FS-FFE improves eye openings by 2.25 times compared with the conventional design using a 50- $\Omega $ TX impedance with 1-UI spacing FFE.
Original language | English |
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Pages (from-to) | 184-195 |
Number of pages | 12 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 59 |
Issue number | 1 |
DOIs | |
State | Published - Jan 1 2024 |
Externally published | Yes |
Keywords
- Four-level pulse-amplitude modulation ({PAM-4})
- fractionally spaced feedforward equalization (FS-FFE)
- high-speed I/O
- relaxed termination
- switching-jitter compensation