A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications

Seki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, Kwonwoo Kang, Sangho Kim, Takahiro Nomiyama, Ji Seon Paek, Jongwoo Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents an analog assisted digital LDO achieving high current density and fast response characteristic. A current comparator based control method enables over 10x ratio of digital current over analog current for high current density regardless of PVT condition. The proposed LDO in 3nm GAAFET CMOS technology demonstrated current density of 34.15A/mm2 and fast transient characteristic of 38mV droop at 1A/1ns load current condition.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages190-191
Number of pages2
ISBN (Electronic)9781665497725
DOIs
StatePublished - 2022
Externally publishedYes
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: Jun 12 2022Jun 17 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period06/12/2206/17/22

Keywords

  • DLDO
  • Digital LDO
  • analog assisted digital LDO
  • hybrid LDO

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