A 3D Implementation of Convolutional Neural Network for Fast Inference

Narasinga Rao Miniskar; Pruek Vanna-Iampikul; Aaron Young; Sung Kyu Lim; Frank Liu; Jieun Yoo; Corrinne Mills; Nhan Tran; Farah Fahim; Jeffrey S. Vetter

doi:10.1109/ISCAS46773.2023.10181622

A 3D Implementation of Convolutional Neural Network for Fast Inference

Narasinga Rao Miniskar, Pruek Vanna-Iampikul, Aaron Young, Sung Kyu Lim, Frank Liu, Jieun Yoo, Corrinne Mills, Nhan Tran, Farah Fahim, Jeffrey S. Vetter

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.

Original language	English
Title of host publication	ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665451093
DOIs	https://doi.org/10.1109/ISCAS46773.2023.10181622
State	Published - 2023
Event	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States Duration: May 21 2023 → May 25 2023

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2023-May
ISSN (Print)	0271-4310

Conference

Conference	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/Territory	United States
City	Monterey
Period	05/21/23 → 05/25/23

Funding

V. ACKNOWLEDGEMENT This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan).

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10.1109/ISCAS46773.2023.10181622

Cite this

Miniskar, N. R., Vanna-Iampikul, P., Young, A., Lim, S. K., Liu, F., Yoo, J., Mills, C., Tran, N., Fahim, F., & Vetter, J. S. (2023). A 3D Implementation of Convolutional Neural Network for Fast Inference. In ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2023-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS46773.2023.10181622

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title = "A 3D Implementation of Convolutional Neural Network for Fast Inference",

abstract = "Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.",

author = "Miniskar, {Narasinga Rao} and Pruek Vanna-Iampikul and Aaron Young and Lim, {Sung Kyu} and Frank Liu and Jieun Yoo and Corrinne Mills and Nhan Tran and Farah Fahim and Vetter, {Jeffrey S.}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",

year = "2023",

doi = "10.1109/ISCAS46773.2023.10181622",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings",

}

Miniskar, NR, Vanna-Iampikul, P, Young, A, Lim, SK, Liu, F, Yoo, J, Mills, C, Tran, N, Fahim, F & Vetter, JS 2023, A 3D Implementation of Convolutional Neural Network for Fast Inference. in ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2023-May, Institute of Electrical and Electronics Engineers Inc., 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, United States, 05/21/23. https://doi.org/10.1109/ISCAS46773.2023.10181622

A 3D Implementation of Convolutional Neural Network for Fast Inference. / Miniskar, Narasinga Rao; Vanna-Iampikul, Pruek; Young, Aaron et al.
ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2023-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 3D Implementation of Convolutional Neural Network for Fast Inference

AU - Miniskar, Narasinga Rao

AU - Vanna-Iampikul, Pruek

AU - Young, Aaron

AU - Lim, Sung Kyu

AU - Liu, Frank

AU - Yoo, Jieun

AU - Mills, Corrinne

AU - Tran, Nhan

AU - Fahim, Farah

AU - Vetter, Jeffrey S.

PY - 2023

Y1 - 2023

N2 - Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.

AB - Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.

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U2 - 10.1109/ISCAS46773.2023.10181622

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M3 - Conference contribution

AN - SCOPUS:85167699029

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023

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ER -

Miniskar NR, Vanna-Iampikul P, Young A, Lim SK, Liu F, Yoo J et al. A 3D Implementation of Convolutional Neural Network for Fast Inference. In ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS46773.2023.10181622

A 3D Implementation of Convolutional Neural Network for Fast Inference

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