@inproceedings{6dab15e3252e4ab795d1317ed7e5fb3e,
title = "A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces",
abstract = "This paper presents a 20Gb/s/pin single-ended PAM-4 transceiver with advanced switching jitter compensation (SWJC) technique. The SWJC operates independently of equalization, hence further improving timing margin from 0.26UI to 0.39UI at a Ie-I2 BER. The proposed pre-channel SWJC at a transmitter side minimizes switching jitter (SWJ) of middle eye, modulating the transitions of top and bottom eyes in a beneficial way for SWJC at a receiver side. Ultimately, along with the proposed SWJC technique, the timing margins improved by SWJC at a receiver side are further increased, having overheads only 1.6% in power and 0.22% in area.",
keywords = "amplifier biasing, memory interface, PAM-4 transceiver, single-ended, switching jitter compensation",
author = "Kyunghwan Min and Jahoon Jin and Lee, {Soo Min} and Sodam Ju and Jisu Yook and Jihoon Lee and Yunji Hong and Park, {Sung Sik} and Kim, {Sang Ho} and Jongwoo Lee and Hyungjong Ko",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 ; Conference date: 16-06-2024 Through 20-06-2024",
year = "2024",
doi = "10.1109/VLSITechnologyandCir46783.2024.10631482",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024",
}