A 1.7Gbps DLL-based Clock Data Recovery in 0.35μm CMOS

Sang Ho Kim, Hyung Min Park, Tae Ho Kim, Jin Ku Kang, Jin Ho Kim, Jae Youl Lee, Yoon Kyung Choi, Myunghee Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a DLL(Delay Locked Loop)-based CDR(Clock Data Recovery) design with nB(n+2)B data formatting scheme. Due to the proposed data formatting scheme, the CDR does not require the external reference clock. The proposed nB(n+2)B data formatting scheme is done by inserting the '01' pattern in every N-bit data. To prove the feasibility of the scheme, a 1.7Gbps CDR is designed, simulated and fabricated. The proposed CDR achieves less jitter due to the DLL structure. The proposed 1.7Gbps CDR with the 10B12B data formatting consumes approximately 8mA under 3.3V power supply using 0.35m CMOS process.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2010
Pages84-87
Number of pages4
DOIs
StatePublished - 2010
Externally publishedYes
Event23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
Duration: Sep 27 2010Sep 29 2010

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference23rd IEEE International SOC Conference, SOCC 2010
Country/TerritoryUnited States
CityLas Vegas, NV
Period09/27/1009/29/10

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