A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC

Min Gyu Kim; Gil Cho Ahn; Pavan Kumar Hanumolu; Sang Hyeon Lee; Sang Ho Kim; Seung Bin You; Jae Whui Kim; Gabor C. Temes; Un Ku Moon

doi:10.1109/JSSC.2008.920329

A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC

Min Gyu Kim, Gil Cho Ahn, Pavan Kumar Hanumolu, Sang Hyeon Lee, Sang Ho Kim, Seung Bin You, Jae Whui Kim, Gabor C. Temes, Un Ku Moon

Research output: Contribution to journal › Article › peer-review

58 Scopus citations

Abstract

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 μm CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

Original language	English
Article number	4494661
Pages (from-to)	1195-1205
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	43
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2008.920329
State	Published - May 2008
Externally published	Yes

Funding

Manuscript received July 17, 2007; revised December 13, 2007. This work was supported by Samsung Electronics, and in part by the National Science Foundation under NSF CAREER CCR-0133530.

Keywords

Audio ADC
Delta-sigma ADC
Double sampling
Low voltage
Switched-RC

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10.1109/JSSC.2008.920329

Cite this

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abstract = "A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 μm CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.",

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AU - You, Seung Bin

AU - Kim, Jae Whui

AU - Temes, Gabor C.

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A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC

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